This invention is directed to the generation of control signals for causing various components of a computer system to perform an operation. The entire contents of my earlier application, Ser. No. 959,038 filed Nov. 8, 1978, now U.S. Pat. No. 4,316,244, is incorporated by reference herein by this reference hereto.
In this invention, a particular macroinstruction, Load Accumulator (LDA), is logically deciphered to generate a first control signal which is then used to generate control signals depending upon the contents thereof to control parts of the computer in order to cause a word in memory to be copied from memory and be placed in an accumulator. The LDA macroinstruction places the word in memory addressed by this effective address, E in the user-specified accumulator. The previous contents of the memory location remain unchanged. In the LDA instruction "AC" (bits 3 and 4) indicates one of the four accumulators in the computer in which the data in memory is to be read into. Bits 5 to 15 are used for effective address calculations to determine the position of the information in memory to be placed in the designated accumulator. In the LDA macroinstruction bit 5 is called the "indirect bit", bits 6 and 7 are called the "index bits", and bits 8-15 are called the "displacement bits".
If the index bits are 00, the displacement is used as an unsigned 8-bit number to address one of the first 256.sub.10 words in memory. This is called "page zero addressing" and this first block of 256 words is known as "page zero".
If the index bits are 01, the displacement is treated as a signed, two's complement number, which is added to the address of the instruction to produce a memory address. This is called "relative addressing". By relative addressing, any instruction which uses the effective address calculation can directly address any word in storage whose address is in the range -128.sub.10 to +127.sub.10 from the instruction.
If the index bits are 10, accumulator 2 is used as an index register. If the index bits are 11, accumulator 3 is used as an index register. In this form of word addressing, known as "index register addressing", the displacement is treated as a signed, two's complement number which is added to the contents of the selected index register to produce a memory address. In index register addressing the addition of the displacement to the contents of index register does not change the value contained in the index register.
The result of the addition performed in relative addressing and index register addressing is "clipped" to 15 bits. In other words, the high order bit of the result is set to 0. For example, if accumulator 2 is to be used as an index register and contains the number 077774.sub.8, and the displacement bits contain the number 012.sub.8, then the result of the addition would be 000006.sub.8, not 100006.sub.8.
After one of the three types of addresses has been computed from the index and displacement bits, the indirect bit is tested. If this bit is zero, the address already computed is taken as the effective address. If the indirect bit is one, the word addressed by the result of the index and displacement bits is assumed to contain an address. In this word bit 0 is the indirect bit and bits 1-15 contain an address. If bit 0 of the reference word is 1, another level of indirection is indicated, and bits 1-15 contain the address of the next word in the indirection chain. The processor will continue to follow this chain of indirect addresses until a word is retrieved with bit 0 set to 0. Bits 1-15 of this word are taken to be the effective address.
The recognition of index bits 6 and 7 as well as bits 0 to 2 are used in this invention to generate microcode control signals (.mu. or microinstruction) to cause the storing of data at a particular memory address to be stored in designated accumulators. The control signals so generated comprise fifty-six (56) bit words in the embodiment shown with certain of the bits being provided to various computer subsystems to effect the transfer of information from memory. Since the invention herein resides in the generating of specific control signals which are thereafter handled in a routine manner the further use of these control signals will not be discussed in detail.